Target CPU |
T1020, T1030, T1040, T1050, Xtensa LX, Xtensa6, Xtensa7, Xtensa LX2, LX3, LX4 Diamond Standard Processors (Supports the ASIC with the on-chip debugging interface) 106Micro, 108Mini, 212GP, 232L, 570T, 545CK, 330HiFi, 388VDO Note: The EJ-SCT Debugger for Xtensa LX supports Xtensa6 and Diamond Standard Processors, but does not support the MMU capability of these CPUs. |
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Target Vcc |
Vcc= +1.8 V to 3.6 V |
Memory & I/O | Entire space is available to the User. |
Interrupts | Both internal and external interrupts are available to the User. |
Breakpoints and Break Options |
Execution address break options: ・Hardware breakpoints: Instruction:2 points, Data: 2 points* Execution instruction address and memory access can be specified. * The number of hardware breakpoints (BP) will be specified when configuring the CPU. * Upon configuring the CPU, 2 instruction execution addresses and 2 data access addresses must be specified. ・Unlimited software breakpoints Other break options: ・Forced break from the debugger |
Flash Memory |
・Download to target external Flash memory ・Possible to write to not-supported flash memory when users make a custom program ・Stand-alone writer capability Without a command from the computer, users can download to flash memory by recording flash memory writing script into the attached MicroSD. (Two different operation scripts can be recorded) |
Trace feature |
Regarding the trace feature, WATCHPOINT debugger can support the XtensaLX feature that installs the trace feature. Please contact us about more details about the trace feature. |
Tensilica |
C Compiler provided by Tensilica when configuring CPU |
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Support OS | |||
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TOPPERS |
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HOST OS |
Windows 7 (32/64bit) Windows Vista (32/64bit) |
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Memory | Minimum memory requirements are amount of memory recommended for each operating system by the operating systems vendor. |
Hard disk drive | 50MB for installation |
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