EJ-SCT DBG ARM - Specifications | Sohwa & Sophia Technologies

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EJ-SCT Debugger ARM Series [Discontinued Products]

ejsct

RoHS

EJ-SCT is an eco tool for new age. It not only can debug many CPUs from different makers on one common platform, but also can use JTAG emulator/ Stand-alone writer on the same platform. WATCHPOINT supports both single core ARM7/9/11/Cortex (A15,A9,A8,R4,M3) and multiple core. Since the hardware can be re-used, large quantities of H/W for application S/W developments is not necessary any more.
[Discontinued Products]

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EJ-SCT ARM/ARM Multi Core


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Specifications

Target CPU
ARM7 Core Series:
 ARM7TDMI, ARM7TDMI-S, ARM710T, ARM720T, ARM740T, .etc

ARM9 Core Series:
 ARM9TDMI, ARM9TDMI-S, ARM910T, ARM920T, ARM940T, ARM9E, ARM946E, ARM966E, ARM922, ARM925,
 ARM926, .etc

ARM11 Core Series:
 ARM1136, ARM1176, .etc

Cortex Core Series:
 A15, A9,  MPCore, A8, R4, M0/M3/M4
Target Vcc Vcc= 0.8 V to 5.0 V
Memory space Entire space is available to user
Interrupts All interrupts are available to user
Breakpoint
The following conditions can be set.
  - Hardware Breakpoints

     ARM7/ARM9 core                        : Max. 2 points on instruction execution address, memory access or data
      * When one of the following functions is in use as for ARM7/ARM9 core, release one hardware breakpoint.
         [Software breakpoint, PASS step, Step out, or COME]


     ARM11 core                                : Max. 7 points
                                                           3 on instruction execution address, 2 on memory access and 2 on others

     Cortex core  (A15)                    : 5 on instruction execution address and 4 on memory access
                           (A8/A9 MPCore)  : 5 on instruction execution address and 2 on memory access
                           (R4)                      : 7 on instruction execution address and 8 on memory access
                           (M0)                     : 4 on instruction execution address
                           (M3/M4)              : 5 on instruction execution address

 - Software Breakpoints : Unlimited software breakpoints can be set for RAM and Flash memory

 - Other break : Forced break from debugger
Trace For ETB capability : Optional WATCHPOINT add-on software is available.
SWD / SWV SWD is supported by Cortex-A/R/M series. SWV is supported only by Cortex-M series.
Flash memory download It is possible to download a user program directly to flash memory on target board by debugger

Supported Tool Chains

WATCHPOINT supports the following compilers and OS.
Please contact Sohwa & Sophia Technologies for the latest tool chain information.

Compilers

ARM MDK-ARM, DS-5
IAR EWARM
Green Hills GHS
GAIO XCC-V
GNU GCC
Metaware High C/C++/EC++ for ARM

Supported OS

Support OS
μ-T-Kernel/Cortex-M3,M4 μT-REALOS/M3
Keil RTX/Cortex-M3 UDEOS4/Cortex-M3
μC3/Standard TOPPERS/JSP G-OS NORTi4
Thread X/Cortex-M3 Other ITRON OS
Linux L4 μ-kernel
Windows CE
VxWorks Symbian OS
-

System requirements for WATCHPOINT® Debugger

HOST OS
Windows 7      (32/64bit)
Windows Vista (32/64bit)

Memory
The amount of memory recommended for each OS by OS vendor.
Hard disk drive
 At least 500MB of free hard disk space when installing.
* The names of products and services are trademarks or registered trademarks of their respective owners.
* Specifications and configurations are subject to change without notice.

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