EJ-SCT DBG MeP - Specifications | Sohwa & Sophia Technologies

EJ-SCT Debugger MeP Series [Discontinued Products]

ejsct

RoHS

EJ-SCT is an eco tool for new age. It not only can debug many CPUs from different makers on one common platform, but also can use JTAG emulator/ Stand-alone writer on the same platform.
WATCHPOINT supports MeP(Media embedded Processor) core.
[Discontinued Products]

WATCHPOINT(Software)

EJ-SCT_MeP

Specifications

Target CPU	MeP core
Target Vcc	Vcc= +1.2 V to 3.6 V
Memory & I/O	Entire space is available to the User.
Interrupts	Both internal and external interrupts are available to the User.
Breakpoints & Break Options	Breakpoints can be set as follows, • 2 hardware breakpoints (1, 2) Execution instruction address: 1 point Data access : 1 point For C5 core: Execution instruction address: Max 4 point Data access : Max 4point • Unlimited software breakpoints • Other break options: Forced break from Debug Monitor 1: In the area where Software breakpoints are not available, when Step Over, Step Out, or Come to function is in use, release 1 hardware breakpoint. 2: The number of hardware breakpoints may change depending on the CPU core design.
Flash Memory	Download a user program directly to flash memory on target board by debugger
Others	(Resetout-) terminal can be set at Low level by the Reset command from the debugger. (PRUNout) terminal to indicate program execution can be specified at Low or High level.

Supported Tool Chains

WATCHPOINT supports the following compilers and OS.
Please contact Sohwa & Sophia Technologies for the latest tool chain info.

Compilers:

GNU	GCC

Supported OS

Support OS
iTRON	-	-	-

System requirements for WATCHPOINT^® Debugger

HOST OS	Windows 7 (32/64bit) Windows Vista (32/64bit)
Memory	Minimum memory requirements are amount of memory recommended for each operating system by the operating systems vendor.
Hard disk drive	At least 100MByte of free hard disk space

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* Product specifications are subject to change without notice.